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| FAN7888 -- 3 Half-Bridge Gate-Drive IC May 2008 FAN7888 3 Half-Bridge Gate-Drive IC Features Floating Channel for Bootstrap Operation to +200V Typically 350mA/650mA Sourcing/Sinking Current Driving Capability for All Channels 3 Half-Bridge Gate Driver Extended Allowable Negative VS Swing to -9.8V for Signal Propagation at VBS=15V Matched Propagation Delay Time Maximum 50ns 3.3V and 5V Input Logic Compatible Built-in Shoot-Through Prevention Circuit for All Channels with Typically 270ns Dead Time Built-in Common Mode dv/dt Noise Canceling Circuit Built-in UVLO Functions for All Channels Description The FAN7888 is a monolithic three half-bridge gate-drive IC designed for high-voltage, high-speed driving MOSFETs and IGBTs operating up to +200V. Fairchild's high-voltage process and common-mode noise canceling technique provide stable operation of high-side drivers under high-dv/dt noise circumstances. An advanced level-shift circuit allows high-side gate driver operation up to VS = -9.8V (typical) for VBS =15V. The UVLO circuits prevent malfunction when VDD and VBS are lower than the specified threshold voltage. Output drivers typically source/sink 350mA/650mA, respectively, which is suitable for three-phase half-bridge applications in motor drive systems. Applications 3-Phase Motor Inverter Driver 20-SOIC Ordering Information Part Number FAN7888M FAN7888MX Package 20-SOIC Operating Temperature Range -40C to +125C Packing Method Tube Tape & Reel All packages are lead free per JEDEC: J-STD-020B standard. (c) 2008 Fairchild Semiconductor Corporation FAN7888 * Rev. 1.0.0 www.fairchildsemi.com FAN7888 -- 3 Half-Bridge Gate-Drive IC Typical Application Circuit +15V Up to 200V UU 1 HIN1 VB1 20 UL 2 LIN1 HO1 VS1 19 VU 3-Phase BLDC Motor Controller VL 3 HIN2 18 VS1 Q1 Q3 Q5 FAN7888 Q1 Q3 Q5 4 LIN2 LO1 17 WU 5 HIN3 VB2 16 VS1 IU U WL 6 LIN3 HO2 15 3-Phase Inverter VS2 Q4 Q6 Q2 VS3 Q4 Q6 Q2 VS2 7 LO3 VS2 14 IV V W 8 VS3 LO2 13 IW 9 HO3 VB3 VDD 12 GND 11 10 VS3 FAN7888 Rev.00 Figure 1. 3-Phase BLDC Motor Drive Application Internal Block Diagram VB1 UVLO DRIVER PULSE GENERATOR HO1 RR S UHIN HIN1 NOISE CANCELLER Q VS1 VDD_UVLO HIN2 UVLO DRIVER VDD SCHMITT TRIGGER INPUT ULIN HIN3 VDD DELAY LO1 GND LIN1 SHOOT-THOUGH PREVENTION VDD U Phase Driver VB2 LIN2 VHIN VLIN LIN3 V Phase Driver HO2 VS2 LO2 CONTROL LOGIC VDD WHIN WLIN VB3 W Phase Driver HO3 VS3 LO3 FAN7888 Rev.01 Figure 2. Functional Block Diagram (c) 2008 Fairchild Semiconductor Corporation FAN7888 * Rev.1.0.0 www.fairchildsemi.com 2 FAN7888 -- 3 Half-Bridge Gate-Drive IC Pin Configuration HIN1 1 LIN1 2 HIN2 3 20 VB1 19 HO1 18 VS1 FAN7888 LIN2 4 HIN3 5 LIN3 6 LO3 7 VS3 8 17 LO1 16 VB2 15 HO2 14 VS2 13 LO2 12 VDD 11 GND HO3 9 VB3 10 FAN7888 Rev.00 Figure 3. Pin Configuration (Top View) Pin Definitions Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name HIN1 LIN1 HIN2 LIN2 HIN3 LIN3 LO3 VS3 HO3 VB3 GND VDD LO2 VS2 HO2 VB2 LO1 VS1 HO1 VB1 Description Logic input 1 for high-side gate 1 driver Logic input 1 for low-side gate 1 driver Logic input 2 for high-side gate 2 driver Logic input 2 for low-side gate 2 driver Logic input 3 for high-side gate 3 driver Logic input 3 for low-side gate 3 driver Low-side gate driver 3 output High-side driver 3 floating supply offset voltage High-side driver 3 gate driver output High-side driver 3 floating supply voltage Ground Logic and all low-side gate drivers power supply voltage Low-side gate driver 2 output High-side driver 2 floating supply offset voltage High-side driver 2 gate driver output High-side driver 2 floating supply voltage Low-side gate driver 1 output High-side driver 1 floating supply offset voltage High-side driver 1 gate driver output High-side driver 1 floating supply voltage (c) 2008 Fairchild Semiconductor Corporation FAN7888 * Rev.1.0.0 www.fairchildsemi.com 3 FAN7888 -- 3 Half-Bridge Gate-Drive IC Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA=25C, unless otherwise specified. Symbol VB VS VHO1,2,3 VDD VLO1,2,3 VIN dVS/dt PD JA TJ TS Notes: Parameter High-side Floating Supply Voltage of VB1,2,3 High-side Floating Supply Offset Voltage of VS1,2,3 High-side Floating Output Voltage Low-side and Logic-fixed Supply Voltage Low-side Output Voltage Logic Input Voltage (HIN1,2,3 and LIN1,2,3) Allowable Offset Voltage Slew Rate Power Dissipation(1)(2)(3) Thermal Resistance, Junction-to-ambient Junction Temperature Storage Temperature Min. -0.3 VB1,2,3-25 VS1,2,3-0.3 -0.3 -0.3 -0.3 Max. 225.0 VB1,2,3+0.3 VB1,2,3+0.3 25.0 VDD+0.3 VDD+0.3 50 1.8 80 +150 Unit V V V V V V V/ns W C/W C C -55 +150 1. Mounted on 76.2 x 114.3 x 1.6mm PCB (FR-4 glass epoxy material). 2. Refer to the following standards: JESD51-2: Integral circuits thermal test method environmental conditions - natural convection JESD51-3: Low effective thermal conductivity test board for leaded surface-mount packages. 3. Do not exceed PD under any circumstances. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VB1,2,3 VS1,2,3 VDD VHO1,2,3 VLO1,2,3 VIN TA Parameter High-side Floating Supply Voltage High-side Floating Supply Offset Voltage Supply Voltage High-side Output Voltage Low-side Output Voltage Logic Input Voltage (HIN1,2,3 and LIN1,2,3) Ambient Temperature Min. VS1,2,3+10 6-VDD 10 VS1,2,3 GND GND -40 Max. VS1,2,3+20 200 20 VB1,2,3 VDD VDD +125 Unit V V V V V V C (c) 2008 Fairchild Semiconductor Corporation FAN7888 * Rev.1.0.0 www.fairchildsemi.com 4 FAN7888 -- 3 Half-Bridge Gate-Drive IC Electrical Characteristics VBIAS (VDD, VBS1,2,3) = 15.0V, TA = 25C, unless otherwise specified. The VIN and IIN parameters are referenced to GND. The VO and IO parameters are referenced to GND and VS1,2,3 and are applicable to the respective outputs LO1,2,3 and HO1,2,3. Symbol IQDD IPDD1,2,3 VDDUV+ VDDUVVDDHYS Characteristics Quiescent VDD Supply Current Operating VDD Supply Current for each Channel VDD Supply Under-Voltage Positive-going Threshold VDD Supply Under-Voltage Negative-going Threshold VDD Supply Under-Voltage Lockout Hysteresis Quiescent VBS Supply Current for each Channel Operating VBS Supply Current for each Channel VBS Supply Under-Voltage Positive-going Threshold VBS Supply Under-Voltage Negative-going Threshold VBS Supply Under-Voltage Lockout Hysteresis Offset Supply Leakage Current High-level Output Voltage, VBIAS-VO Low-level Output Voltage, VO Output HIGH Short-circuit Pulsed Current(4) Current(4) Output LOW Short-circuit Pulsed Condition VLIN1,2,3=0V or 5V fLIN1,2,3=20kHz, rms Value VDD=Sweep, VBS=15V VDD=Sweep, VBS=15V VDD=Sweep, VBS=15V Min. Typ. Max. Unit 160 500 7.2 6.8 8.2 7.8 0.4 350 900 9.0 8.5 A A V V V LOW SIDE POWER SUPPLY SECTION BOOTSTRAPPED POWER SUPPLY SECTION IQBS1,2,3 IPBS1,2,3 VBSUV+ VBSUVVBSHYS ILK VOH VOL IO+ IOVS VHIN1,2,3=0V or 5V fHIN1,2,3=20kHz, rms Value VDD=15V, VBS=Sweep VDD=15V, VBS=Sweep VDD=15V, VBS=Sweep VB1,2,3=VS1.2.3=200V IO=20mA IO=20mA VO=0V, VIN=5V with PW<10s 250 350 650 -9.8 -7.0 VO=15V, VIN=0V with PW<10s 500 7.2 6.8 50 400 8.2 7.8 0.4 10 1.0 0.6 120 800 9.0 8.5 A A V V V A V V mA mA V GATE DRIVER OUTPUT SECTION Allowable Negative VS Pin Voltage for IN Signal Propagation to HO Logic "1" Input Voltage Logic "0" Input Voltage Logic "1" Input Bias Current Logic "0" Input Bias Current(4) Input Pull-down Resistance VIN=5V VIN=0V 100 2.5 LOGIC INPUT SECTION (HIN, LIN) VIH VIL IIN+ IINRIN Note: 4. This parameter is guaranteed by design. V 1.0 25 200 50 2.0 300 V A A K (c) 2008 Fairchild Semiconductor Corporation FAN7888 * Rev.1.0.0 www.fairchildsemi.com 5 FAN7888 -- 3 Half-Bridge Gate-Drive IC Dynamic Electrical Characteristics TA=25C, VBIAS (VDD, VBS1,2,3) = 15.0V, VS1,2,3 = GND, CLoad = 1000pF unless otherwise specified. Symbol tON tOFF tR tF MT1 MT2 DT MDT Parameter Turn-on Propagation Delay Turn-off Propagation Delay Turn-on Rise Time Turn-off Fall Time Turn-on Delay Matching I tON(H) -tOFF(L) I Turn-off Delay Matching I tOFF(H) -tON(L) I Dead Time Dead-time Matching I tDT1 -tDT2 I Conditions VS1,2,3=0V VS1,2,3=0V Min. Typ. Max. Unit 130 150 50 30 220 240 120 80 50 50 ns ns ns ns ns ns ns ns 100 270 440 60 (c) 2008 Fairchild Semiconductor Corporation FAN7888 * Rev.1.0.0 www.fairchildsemi.com 6 FAN7888 -- 3 Half-Bridge Gate-Drive IC Typical Characteristics 250 300 250 200 tON [ns] 150 tOFF [ns] 200 150 100 100 50 50 0 -40 0 -40 -20 0 20 40 60 80 100 120 -20 0 20 40 60 80 100 120 Temperature [C] Temperature [C] Figure 4. Turn-on Propagation Delay vs. Temp. Figure 5. Turn-off Propagation Delay vs. Temp. 120 100 80 60 40 20 0 -40 100 80 tR [ns] tF [ns] -20 0 20 40 60 80 100 120 60 40 20 0 -40 -20 0 20 40 60 80 100 120 Temperature [C] Temperature [C] Figure 6. Turn-on Rise Time vs. Temp. Figure 7. Turn-off Fall Time vs. Temp. 50 50 40 40 MT1 [ns] 30 MT2 [ns] -20 0 20 40 60 80 100 120 30 20 20 10 10 0 -40 0 -40 -20 0 20 40 60 80 100 120 Temperature [C] Temperature [C] Figure 8. Turn-on Delay Matching vs. Temp. Figure 9. Turn-off Delay Matching vs. Temp. (c) 2008 Fairchild Semiconductor Corporation FAN7888 * Rev.1.0.0 www.fairchildsemi.com 7 FAN7888 -- 3 Half-Bridge Gate-Drive IC Typical Characteristics (Continued) 500 60 50 400 DT [ns] MDT [ns] -20 0 20 40 60 80 100 120 40 30 20 10 300 200 100 -40 0 -40 -20 0 20 40 60 80 100 120 Temperature [C] Temperature [C] Figure 10. Dead Time vs. Temp. Figure 11. Dead-Time Matching vs. Temp. 350 300 120 100 IQDD [A] IQBS [A] -20 0 20 40 60 80 100 120 250 200 150 100 50 0 -40 80 60 40 20 0 -40 -20 0 20 40 60 80 100 120 Temperature [C] Temperature [C] Figure 12. Quiescent VDD Supply Current vs. Temp. Figure 13. Quiescent VBS Supply Current vs. Temp. 1000 1000 800 800 IPDD [A] 600 IPBS [A] -20 0 20 40 60 80 100 120 600 400 400 200 200 0 -40 0 -40 -20 0 20 40 60 80 100 120 Temperature [C] Temperature [C] Figure 14. Operating VDD Supply Current vs. Temp. Figure 15. Operating VBS Supply Current vs. Temp. (c) 2008 Fairchild Semiconductor Corporation FAN7888 * Rev. 1.0.0 www.fairchildsemi.com 8 FAN7888 -- 3 Half-Bridge Gate-Drive IC Typical Characteristics (Continued) 9.0 9.0 8.5 8.5 VDDUV+ [V] 8.0 VDDUV- [V] -20 0 20 40 60 80 100 120 8.0 7.5 7.5 7.0 -40 7.0 -40 -20 0 20 40 60 80 100 120 Temperature [C] Temperature [C] Figure 16. VDD UVLO+ vs. Temp. Figure 17. VDD UVLO- vs. Temp. 9.0 9.0 8.5 8.5 VBSUV+ [V] 8.0 VBSUV- [V] -20 0 20 40 60 80 100 120 8.0 7.5 7.5 7.0 -40 7.0 -40 -20 0 20 40 60 80 100 120 Temperature [C] Temperature [C] Figure 18. VBS UVLO+ vs. Temp. Figure 19. VBS UVLO- vs. Temp. 1.0 0.60 0.8 0.45 VOH [V] VOL [V] -20 0 20 40 60 80 100 120 0.6 0.30 0.4 0.2 0.15 0.0 -40 0.00 -40 -20 0 20 40 60 80 100 120 Temperature [C] Temperature [C] Figure 20. High-Level Output Voltage vs. Temp. Figure 21. Low-Level Output Voltage vs. Temp. (c) 2008 Fairchild Semiconductor Corporation FAN7888 * Rev. 1.0.0 www.fairchildsemi.com 9 FAN7888 -- 3 Half-Bridge Gate-Drive IC Typical Characteristics (Continued) 3.0 2.5 2.0 3.0 2.5 2.0 VIH [V] 1.5 1.0 0.5 0.0 -40 VIL [V] -20 0 20 40 60 80 100 120 1.5 1.0 0.5 0.0 -40 -20 0 20 40 60 80 100 120 Temperature [C] Temperature [C] Figure 22. Logic High Input Voltage vs. Temp. Figure 23. Logic Low Input Voltage vs. Temp. 50 -7 40 -8 IIN+ [A] 20 VS [V] -20 0 20 40 60 80 100 120 30 -9 -10 10 -11 0 -40 -12 -40 -20 0 20 40 60 80 100 120 Temperature [C] Temperature [C] Figure 24. Logic Input High Bias Current vs. Temp. Figure 25. Allowable Negative VS Voltage vs. Temp. 500 400 RIN [k] 300 200 100 0 -40 -20 0 20 40 60 80 100 120 Temperature [C] Figure 26. Input Pull-down Resistance vs. Temp. (c) 2008 Fairchild Semiconductor Corporation FAN7888 * Rev. 1.0.0 www.fairchildsemi.com 10 FAN7888 -- 3 Half-Bridge Gate-Drive IC Application Information 1. Protection Function 1.1 Under-Voltage Lockout (UVLO) The high- and low-side drivers include under-voltage lockout (UVLO) protection circuitry for each channel that monitors the supply voltage (VDD) and bootstrap capacitor voltage (VBS1,2,3) independently. It can be designed prevent malfunction when VDD and VBS1,2,3 are lower than the specified threshold voltage. The UVLO hysteresis prevent chattering during power supply transitions. 2. Operational Notes The FAN7888 is a three half-bridge gate driver with internal typically 120ns dead-time for the three-phase Brushless DC (BLDC) motor drive system, as shown in Figure 1. Figure 29 shows a switching sequence of 120 electrical commutation for a three-phase BLDC motor drive system. The waveforms are idealized: they assumed that the generated back EMF waveforms are trapezoidal with flat tops of sufficient width to produce constant torque when the line currents are perfectly rectangular 120 electrical degrees with the switching sequence as shown in Figure 29. The operating waveforms of the wey-connection reveal that repeat every 60 electrical degrees, with each 60 segment being "commutated" to another phase, as shown in Figure 29. 1.2 Shoot-Through Prevention Function The FAN7888 has shoot-through prevention circuitry monitoring the high- and low-side control inputs. It can be designed to prevent outputs of high and low side from turning on at same time, as shown Figure 27 and 28. HIN1,2,3/LIN1,2,3 LIN1,2,3/HIN1,2,3 Shoot-Through Prevent HO1,2,3/LO1,2,3 After DT LO1,2,3/HO1,2,3 After DT FAN7888 Rev.00 Figure 27. Waveforms for Shoot-Through Prevention HIN1,2,3/LIN1,2,3 LIN1,2,3/HIN1,2,3 Shoot-Through Prevent HO1,2,3/LO1,2,3 After DT LO1,2,3/HO1,2,3 FAN7888 Rev.00 Figure 28. Waveforms for Shoot-Through Prevention (c) 2008 Fairchild Semiconductor Corporation FAN7888 * Rev.1.0.0 www.fairchildsemi.com 11 FAN7888 -- 3 Half-Bridge Gate-Drive IC Application Information (Continued) -30 0 30 60 90 120 150 180 210 240 270 300 330 Elec o Input / Output HIN / HO1,2,3 LIN / LO1,2,3 Q5 (HIN3) Q6 (LIN2) Q1 (HIN1) Q2 (LIN3) Q3 (HIN2) Q4 (LIN1) Q5 (HIN3) Phase Current IU IV IW Phase Voltage VS1 Phase Back EMF VS2 VS3 Current Flow Direction U V W U V W U V W U V W U V W U V W Figure 29. 120 Commutation Operation Waveforms for 3-Phase BLDC Motor Application Switching Time Definitions HIN1,2,3 /LIN1,2,3 50% 50% tON(H) tR 90% tOFF(H) tF 90% HO1,2,3 10% 10% MT1 90% MT2 90% tOFF(L) LO1,2,3 tON(L) 10% 10% Figure 30. Switching Time Definition (c) 2008 Fairchild Semiconductor Corporation FAN7888 * Rev. 1.0.0 www.fairchildsemi.com 12 FAN7888 -- 3 Half-Bridge Gate-Drive IC Mechanical Dimensions . 13.00 12.60 11.43 20 B 11 A 9.50 10.65 7.60 10.00 7.40 2.25 1 PIN ONE INDICATOR 0.51 0.35 0.25 M 10 1.27 CBA 1.27 0.65 LAND PATTERN RECOMMENDATION 2.65 MAX SEE DETAIL A C 0.33 0.20 0.10 C SEATING PLANE 0.75 0.25 (R0.10) (R0.10) 8 0 X 45 0.30 0.10 NOTES: UNLESS OTHERWISE SPECIFIED GAGE PLANE 0.25 1.27 0.40 (1.40) A) THIS PACKAGE CONFORMS TO JEDEC MS-013, VARIATION AC, ISSUE E B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) CONFORMS TO pdip8_dim.pdf ASME Y14.5M-1994 E) LANDPATTERN STANDARD: SOIC127P1030X265-20L F) DRAWING FILENAME: MKT-M20BREV3 SEATING PLANE DETAIL A SCALE: 2:1 MKT-M20BREV3 Figure 31. 20-Lead Small Outline Package (SOIC) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ (c) 2008 Fairchild Semiconductor Corporation FAN7888 * Rev.1.0.0 www.fairchildsemi.com 13 FAN7888 -- 3 Half-Bridge Gate-Drive IC (c) 2008 Fairchild Semiconductor Corporation FAN7888 * Rev. 1.0.0 www.fairchildsemi.com 14 |
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